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September 15, 2005
Date & Place of MAP&RTS2005
MAP&RTS2005
Dates:
15-16 September, 2005
Venue:
Asia Pacific Import Mart,
West Japan General Exhibition Center, Kitakyushu, JAPAN
Hall Map (Click to enlarge)
Posted by MAP&RTS2005Q : 12:08 AM
September 06, 2005
MAP&RTS2005 Program
You can see the Program of MAP&RTS2005.
PDF file can be downloaded. Program(PDF)
MAP&RTS 2005 PROGRAM
THURSDAY 15 September
13:00～13:15 Opening Remark ・・・・・・・・・・・・Conference Room A
13:15～14:45 SESSION 1: Invited Talks
Chair: Hajime Tomokage (Fukuoka University)
13:15～14:00 1.1 For the Revival of Japanese Semiconductor Industry
Shuichi Otsuka
Hiroshima Elpida Memory, Inc. (Japan)
14:00～14:45 1.2 Greater China’s Big Leap in ICT Industry
Colley Hwang
DigiTimes Publication Inc. (Taiwan)
14:45～15:00 COFFEE BREAK & Reverse Trade Show
15:00～15:40 SESSION 2 : JEITA Program ・・・・・・・・Conference Room A
Chair : Jae-Ho Lee (Hongik University)
15:00～:20 2.1 Jisso to Create the World of Electronics and Information Technology
Hisao Kasuga
NEC Electronics Corporation (Japan)
15:20～15:40 2.2 Printed Wiring Board Technology Roadmap & Embedded Active Devices Technology Trends from Jisso Technology Roadmap 2005
Henry H. Utsunomiya
Interconnection Technologies, Inc.(Japan)
15:40～16:00 COFFEE BREAK & Reverse Trade Show
16:00～ 17:30 SESSION 3 : Package-on-Package Technology・・Conference Room A
Chair : Eddie Ohtsuru (Kyushu University)
16:00～16:20 3.1 Toward the 3D-SiP Era
Morihiro Kada
Sharp Corporation (Japan)
16:20～16:40 3.2 Amkor 3D PKG Development Activity
Jun Taniguchi
Amkor Technology Japan KK. (Japan)
16:40～17:10 3.3 The Third Jisso Revolution “The issues and the future view of POP three dimensional Jisso”
Yusuke Yamamoto
Panasonic Factory Solutions Co., Ltd. (Japan)
17:10～17:30 3.4 Characteristics of New Solder Paste for Three dimensional Package
Yoshinori Takagi
Senju Metal Industry Co., Ltd. (Japan)
17:30～17:50 COFFEE BREAK & Reverse Trade Show
17:50～19:30 SESSION 4 : Advanced Design, Fabrication and Evaluation
Chair : Donghwan Kim (Korea University) ・・・・・・Conference Room A
17:50～18:10 4.1 Integration of 3D-EM Simulation and Measurement
Eiji Tanabe
AET Japan, Inc. (Japan)
18:10～18:30 4.2 Development of a New Confocal Video-Based Measuring System foCoordinate Measurement of 3 Dimensional Features of the State-of-Art Semiconductor Packages
Fusao Shimizu*, Hiroo Tsumuraya*, Shuichi Sakai**
*Nikon Corporation Instruments Company (Japan),
** Nikon Instech Co., Ltd. (Japan)
18:30～18:50 4.3 Demand for High Speed Thermal Shock Testing of Printed Circuit Board
Shinichi Sumiyoshi
INOUEKI CO., LTD (Japan)
18:50～19:10 4.4
EPISIL (Taiwan)
19:10～19:30 4.5 Advanced Analysis Technology Supporting SiP
Ken Sugiura* , Hiroaki Itomine** , Hiroshi Murakami*
*FUKURYO SEMICON ENGINEERING, CORPORATION,
**OLYMPUS CORPORATION (Japan)
19:30～21:00 RECEPTION PARTY ( Conference Room B )
FRIDAY 16 September
09:10～10:10 SESSION 5: Asian Topics ・・・・・・・・・・Conference Room A
Chair: Toru Takahashi (Japan External Trade Organization)
09:10～09:30 5.1 Challenges and Business Opportunities in Electronics Industry in Malaysia
Afifuddin A.Kadir
Malaysian Industrial Development Authority (Malaysia)
09:30～09:50 5.2 Opportunities for IC/Electronics Industries in HK and PRD
S.W Cheung
Hong Kong Science and Technology Parks Corporation (China)
09:50～10:10 5.3 Outline of Kitakyushu Science and Research Park
Yukie Nomi
Kitakyushu Foundation for the Advancement of Industry, Science and Technology (Japan)
10:10～10:40 COFFEE BREAK and Reverse Trade Show
10:40～12:00 SESSION 6: Automobile Design Technology・・Conference Room A
Chair: Todd Takaki (Inoueki Co.,Ltd.)
10:40～11:20 6.1 Automotive Market and Semiconductor Technology Trend
Michio Sato
Freescale Semiconductor Japan Ltd. (Japan)
11:20～11:40 6.2 The Future of car electronics and Testing of semiconductor devices for Automotive
Yasunori Yamaguchi
Teradyne, Inc. (Japan)
11:40~12:00 6.3 Introduction of ENG CMOS Sensor Core IP
T. Abe
Exploitation of Next Generation Co., Ltd. (Japan)
12:00～13:30 LUNCH BREAK and Reverse Trade Show
13:30～14:50 SESSION 7: Simulation and Analysis・・・・・・Conference Room A
Chair: Seiichiro Yoshida (New Japan Radio Co.,Ltd.)
13:30～13:50 7.1 Co-Simulation of Chip and Package for Power Integrity Optimization in High Speed Digital System
S. Seki
ATE Service Corp. (Japan)
13:50～14:10 7.2 Encapsulation of Semiconductors – A Multi-physics Simulation
Sejin Han*, Franco Costa**, Shishir Ray** and Peter K. Kennedy**
*Moldflow Corporation (U.S.A.), **Moldflow Pty. Ltd. (Australia)
14:10～14:30 7.3 Open DFM Visualization Technology - 3D CAD System for DFM
Andres Carrasco*, Masayuki Kayama**
*CAD Design Software (U.S.A.),
**Nagase Electronic Equipment Service Co., Ltd., (Japan)
14:30～14:50 7.4 Introduction of the Thermal Design Tools from Fluent Inc.
Kazuhiro Ogawa
Fluent Asia Pacific Co.,Ltd.,
14:50～15:40 COFFEE BREAK and Reverse Trade Show
13:30～15:10 SESSION 8: Substrate and Board ・・・・・・Conference Room B
Chair: Yangdo Kim (Pusan National University)
13:30～13:50 8.1 High-Frequency Dielectric Properties of Halogen-Free Material for PWBs
Y.Shimada and E.Watanabe
Hitachi Chemical Co.,Ltd. (Japan)
13:50～14:10 8.2 New IC Package Structures for High Speed Chip to Chip Interconnections
Joseph Fjelstad
SiliconPipe, Inc (U.S.A.)
14:10～14:30 8.3 Copper Electroplating on Flexible Substrate for CoF (Chip on Fiilm) Applications
Sung-Sup Byun, Jung-Eun Kang, Jae-Ho Lee
Hongik University (Korea)
14:30～14:50 8.4 PWB Technology for Wafer Probe Cards and Burn-in Boards
Isao Kaneda
Oki Printed Circuits Co.,Ltd. (Japan)
14:50～15:10 8.5
Hajime Fukawa
Minami
15:10～15:40 COFFEE BREAK and Reverse Trade Show
15:40～17:00 SESSION 9: Testing Technology ・・・・・・・Conference Room A
Chair: Fumiaki Shigeoka (Ueno Seiki Co.,Ltd.)
15:40～16:00 9.1 Proposal of SoC Testing -Challenges to Improving QCDS by Integration of
SoC Design and Test-
Norio Kubo
Yokogawa Electric Corporation (Japan)
16:00～16:20 9.2
KYEC (Taiwan)
16:20～16:40 9.3 Approach of the Product Engineering Business
Megumi Nakano
Elia Co., Ltd. (Japan)
16:40～17:00 9.4 Open DFT Yield Solution
Rocky Kobayashi
ATE Service Corp. (Japan)
15:40～17:00 SESSION 10: System-in-a-Package Technology
・・・・・・・・Conference Room B
Chair: Henry H. Utsunomiya (Interconnection Technologies Inc.)
15:40～16:00 10.1 System-in-a-package (SiP) Solution
Mamoru Kajihara
NEC Electronics Corporation (Japan)
16:00～16:20 10.2 Wafer Process Chip Size Package Consisting of Double-Bump Structure for Small-Pin-Count packages
Kaoru Mitsuka, Hiroyuki Kurata, Jun Furukawa, Michiya Takahashi
New Japan Radio Co., Ltd. (Japan)
16:20～16:40 10.3 Trend of WLP Technology and Next Generation Packaging “WLP & EWLP”
Daishi Komatsu
CASIO COMPUTER Co.,Ltd.(Japan)
16:40～17:00 10.4 Introducing "System in Silicon" - New Multichip Technology with Microbump
Naoya Tohyama
System Fabrication Technologies, Inc.(Japan)
17:00～19:00 SESSION 11: Poster Presentation with wines・・・・・・・・Exhibition Hall
Chair: Hiroshi Kido (Kitakyushu University)
Posted by MAP&RTS2005Q : 09:10 PM